WSGR256M16D3DFL

The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs isdouble data rate architecture to achieve high-speedoperation. It is internally configured as an eight bankDRAM.The 4Gb chip is organized as 32Mbit x 16 I/Os x8 bankdevices. These synchronous devices achieve high speeddouble-data-rate transfer rates of up to 1866 Mb/sec/pinfor general applications.The chip is designed to comply with all key DDR3LDRAM key features and all of the control and addressinputs are synchronized with a pair of externally supplieddifferential clocks. Inputs are latched at the cross pointof differential clocks (CK rising and CK# falling). All I/Osare synchronized with differential DQS pair in a sourcesynchronous fashion.These devices operate with a single +1.35V -0.067V /+0.1V power supply and are available in BGA packages.

详细介绍

 JEDEC Standard Compliant
 Power supplies: VDD & VDDQ =+1.35V
 Backward compatible to VDD & VDDQ =+1.5V ±0.075V
 Operating temperature range:

- Normal operating temperature: TC = 0~85°C

- Extended temperature: TC = 85~95°C

 Supports JEDEC clock jitter specification
 Fully synchronous operation
 Fast clock rate: 800/933MHz
 Differential Clock, CK & CK#
 Bidirectional differential data strobe

- DQS & DQS#

 8 internal banks for concurrent operation
 8n-bit prefetch architecture
 Pipelined internal architecture
 Precharge & active power down
 Programmable Mode & Extended Mode registers
 Additive Latency (AL): 0, CL-1, CL-2
 Programmable Burst lengths: 4, 8
 Burst type: Sequential / Interleave
 Output Driver Impedance Control
 Average refresh period

- 8192 cycles/64ms (7.8us at 0°C ≦ TC ≦ +85°C)

- 8192 cycles/32ms (3.9us at +85°C ≦ TC ≦ +95°C)

 Write Leveling
 ZQ Calibration
 Dynamic ODT (Rtt_Nom & Rtt_WR)
 RoHS compliant
 Auto Refresh and Self Refresh
 96-ball 7.5 x 13.5 x 1.2mm FBGA package

- Pb and Halogen Free

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